Sensor With Multiple Sub - radix - 2 SAR ADC Calibration and Residual Column Pattern Noise Correction
نویسندگان
چکیده
Conclusion We developed PFM-ADCs with a novel event-driven CDS technique. Measurement results demonstrated inpixel noise reduction effects of below 1% and a wide dynamic range of 120 dB with an excellent linearity. The ADCs are promising for the pixel-parallel 3-D integrated image sensor with ultimate performances. References [1] R. Funatsu et al., “133Mpixel 60fps CMOS Image Sensor with 32-Column Shared High-Speed Column-Parallel SAR ADCs,” in IEEE Int. SolidState Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2015, pp. 112–113. [2] M. Goto et al., “Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel A/D Converters Fabricated by Direct Bonding of SOI Layers,” in IEEE Int. Electron Devices Meeting (IEDM) Tech. Dig., Dec. 2014, pp. 4.2.1–4.2.4. [3] M. Goto et al., “Pixel-Parallel 3-D Integrated CMOS Image Sensors With Pulse Frequency Modulation A/D Converters Developed by Direct Bonding of SOI Layers,” IEEE Trans. Electron Devices, vol. 62, no. 11, pp. 3530–3535, 2015. [4] M. Goto et al., “In-Pixel A/D Converters with 120dB Dynamic Range Using Event-Driven Correlated Double Sampling for Stacked SOI Image Sensors,” in Proc. IEEE SOI-3D-Subthreshold Microelectron. Technol. Unified Conf. (S3S) Conf., 2016, 6b.3. [5] M. Goto et al., “A Three-Dimensional Integration Technology with Embedded Au Electrodes for stacked CMOS Image Sensors,” in Proc. 2015 Int. Image Sensor Workshop (IISW), 2015, pp. 48–50. [6] F. Andoh, H. Shimamoto, and Y. Fujita, “A Digital Pixel Image Sensor for Real-Time Readout,” IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2123– 2127, 2000. [7] M. White et al., “Characterization of charge-coupled device line and area-array imaging at low light levels,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 1973, pp. 134–135. [8] J. Hynecek, “A New Device Architecture Suitable for High-Resolution and High-Performance Image Sensors,” IEEE Trans. Electron Devices, vol. 35, no. 5, pp. 646–652, 1988. P25 Image Sensor With Multiple Sub-radix-2 SAR ADC Calibration and Residual Column Pattern Noise Correction Daniel Van Blerkom, Steve Huang, Barmak Mansoorian Forza Silicon Corporation, 2947 Bradley St, Suite 130, Pasadena, California, 91107, USA contact: [email protected], +1-626-796-1182 x 111
منابع مشابه
Signal independent digital calibration technique for SAR ADC with one bit redundancy
A digital calibration technique for high resolution SAR ADC with only one redundant conversion bit is presented in this paper. The proposed work employs no extra calibration DAC or input signal as calibration reference. Calibration signal is generated through switching redistribution DAC in two calibration phase, so that calibration accuracy will not be affected by input signal distribution. DA...
متن کاملA Two-Step A/D Conversion and Column Self-Calibration Technique for Low Noise CMOS Image Sensors
In this paper, a 120 frames per second (fps) low noise CMOS Image Sensor (CIS) based on a Two-Step Single Slope ADC (TS SS ADC) and column self-calibration technique is proposed. The TS SS ADC is suitable for high speed video systems because its conversion speed is much faster (by more than 10 times) than that of the Single Slope ADC (SS ADC). However, there exist some mismatching errors betwee...
متن کاملA Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs
This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing nois...
متن کاملTwo-Step Single Slope/SAR ADC with Error Correction for CMOS Image Sensor
Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR) ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit...
متن کاملDesign of a PTC-Inspired Segmented ADC for High-Speed Column-Parallel CMOS Image Sensor
This paper presents a successive approximation ADC (SAR) architecture that takes advantage of the signal-dependent photon shot-noise characteristic of an image sensor. The multi-segmented successive approximation ADC (MS-SAR) applies the sub-ranging technique, where each segment’s conversion step size is scaled according to the photon transfer curve (PTC) of a given pixel. The MS-SAR selects th...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2017